一种新型动态缩放FFT处理器

The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI:10.1109/APCCAS.2004.1412793

Yu-Wei Lin, Chen-Yi Lee

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引用次数: 1

摘要

提出了一种采用基数-8算法和新型矩阵缓冲的FFT处理器。采用新的动态缩放方法，可在8k点FFT中节省64k位的内存。此外，通过数据调度和预取缓冲，我们的FFT处理器可以采用单端口内存。采用0.18 /spl mu/m CMOS工艺，设计制作了8k模式DVB-T系统测试芯片，核心面积为4.84 mm/sup /， 20 MHz时功耗仅为25.2 mW。

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A new dynamic scaling FFT processor

A new FFT processor with radix-8 algorithm and novel matrix buffer is presented in this paper. About 64 K bit memory can be saved in 8 K-point FFT by new dynamic scaling approach. Moreover, with data scheduling and pre-fetched buffering, single-port memory can be adopted in our FFT processor. A test chip for 8 K mode DVB-T system has been designed and fabricated using 0.18 /spl mu/m CMOS process with core area of 4.84 mm/sup 2/ and consumes only 25.2 mW at 20 MHz.

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The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.

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