Accurate System-level TSV-to-TSV Capacitive Coupling Fault Model for 3D-NoC

TSV-based 3D-NoC has been introduced as a viable solution for integrating more cores on a chip, while imposing smaller footprint area and better timing performance as compared to 2D-NoC. However, TSV-to-TSV coupling is increasingly impacting the reliability of 3D-NoCs due to large size of TSVs. Addressing this issue, various resilient approaches have been recently proposed. But they have been evaluated by uniform random distributions fault modelling, which results in 26%-99% inaccuracy. We propose a system-level TSV-to-TSV coupling fault model that models the capacitive coupling effect, considering thermal impact, with circuit-level accuracy. This model can be plugged into any system-level TSV-based 3D-NoC simulator. It is also capable of identifying faulty TSV bundles and evaluating the efficiency of alternative resilient TSV-based 3D-NoC designs at the system-level.