A 2.4-GHz fractional-N frequency synthesizer with noise filtering technique for wireless application

A hybrid fractional-N frequency synthesizer with noise filtering technique for wireless application is implemented with TSMC 0.18 μm CMOS process. In order to reduce the effects of high order delta-sigma modulator (Δ Σ M), and suppress the out-of-band quantization noise, a noise filter is adopted. An integer-N phase-locked loop acts as the noise filter in the feedback path of a fractional-N frequency synthesizer. With supply voltages of 0.9 V for analog circuits and 1.8 V for digital circuits, measured results achieve that output frequency of VCO is tunable from 2.30 to 2.52 GHz, corresponding to 9.1%, a frequency synthesizer phase noise of -113.51 dBc/Hz at 1 MHz offset from carrier frequency of 2.41 GHz, and a overall power consumption of 20 mW. Including pads, the total chip area occupies 0.922 (0.94 × 0.98) mm2.