{"title":"MCM布局的分布式rcl模型","authors":"D. Zhou, F. Tsui, J. Cong, D. Gao","doi":"10.1109/MCMC.1993.302128","DOIUrl":null,"url":null,"abstract":"The authors model high-speed VLSI interconnects by using a generic distributed RLC-tree. Through a detailed analysis of the distributed RLC-tree a two-pole approximation system is established to formulate the performance-driven layout in MCM designs. An in-depth study of the formulated performance-driven layout problem reveals the interplay between the interconnector's performance and its geometrical parameters. The study leads to an A-tree topology to optimize the defined performance-driven layout problem. Significant improvement, an average up to 67% reduction on the interconnection delay, is achieved over large sample MCM designs, as compared with the well known Steiner tree topology.<<ETX>>","PeriodicalId":143140,"journal":{"name":"Proceedings 1993 IEEE Multi-Chip Module Conference MCMC-93","volume":"96 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":"{\"title\":\"A distributed-RCL model for MCM layout\",\"authors\":\"D. Zhou, F. Tsui, J. Cong, D. Gao\",\"doi\":\"10.1109/MCMC.1993.302128\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The authors model high-speed VLSI interconnects by using a generic distributed RLC-tree. Through a detailed analysis of the distributed RLC-tree a two-pole approximation system is established to formulate the performance-driven layout in MCM designs. An in-depth study of the formulated performance-driven layout problem reveals the interplay between the interconnector's performance and its geometrical parameters. The study leads to an A-tree topology to optimize the defined performance-driven layout problem. Significant improvement, an average up to 67% reduction on the interconnection delay, is achieved over large sample MCM designs, as compared with the well known Steiner tree topology.<<ETX>>\",\"PeriodicalId\":143140,\"journal\":{\"name\":\"Proceedings 1993 IEEE Multi-Chip Module Conference MCMC-93\",\"volume\":\"96 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-03-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"16\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 1993 IEEE Multi-Chip Module Conference MCMC-93\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MCMC.1993.302128\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 1993 IEEE Multi-Chip Module Conference MCMC-93","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MCMC.1993.302128","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The authors model high-speed VLSI interconnects by using a generic distributed RLC-tree. Through a detailed analysis of the distributed RLC-tree a two-pole approximation system is established to formulate the performance-driven layout in MCM designs. An in-depth study of the formulated performance-driven layout problem reveals the interplay between the interconnector's performance and its geometrical parameters. The study leads to an A-tree topology to optimize the defined performance-driven layout problem. Significant improvement, an average up to 67% reduction on the interconnection delay, is achieved over large sample MCM designs, as compared with the well known Steiner tree topology.<>
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