{"title":"带正反馈补偿方案的三级放大器","authors":"J. Ramos, M. Steyaert","doi":"10.1109/CICC.2002.1012833","DOIUrl":null,"url":null,"abstract":"A CMOS opamp that can drive large capacitive loads is presented. The technique employs a positive feedback compensation (PFC) to improve frequency response as compared to nested Miller compensation (NMC), allowing the circuit to occupy less silicon area and straightforward design. At 1.5 V, the circuit dissipates 275 /spl mu/W, has more than 100 dB gain, a gain bandwidth of 2.7 MHz and 1.0 V//spl mu/s average slew rate while driving a 130 pF load.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"19","resultStr":"{\"title\":\"Three stage amplifier with positive feedback compensation scheme\",\"authors\":\"J. Ramos, M. Steyaert\",\"doi\":\"10.1109/CICC.2002.1012833\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A CMOS opamp that can drive large capacitive loads is presented. The technique employs a positive feedback compensation (PFC) to improve frequency response as compared to nested Miller compensation (NMC), allowing the circuit to occupy less silicon area and straightforward design. At 1.5 V, the circuit dissipates 275 /spl mu/W, has more than 100 dB gain, a gain bandwidth of 2.7 MHz and 1.0 V//spl mu/s average slew rate while driving a 130 pF load.\",\"PeriodicalId\":209025,\"journal\":{\"name\":\"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)\",\"volume\":\"54 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"19\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2002.1012833\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2002.1012833","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Three stage amplifier with positive feedback compensation scheme
A CMOS opamp that can drive large capacitive loads is presented. The technique employs a positive feedback compensation (PFC) to improve frequency response as compared to nested Miller compensation (NMC), allowing the circuit to occupy less silicon area and straightforward design. At 1.5 V, the circuit dissipates 275 /spl mu/W, has more than 100 dB gain, a gain bandwidth of 2.7 MHz and 1.0 V//spl mu/s average slew rate while driving a 130 pF load.