用于低压操作的13T抗辐射SRAM位单元

L. Atias, A. Teman, A. Fish
{"title":"用于低压操作的13T抗辐射SRAM位单元","authors":"L. Atias, A. Teman, A. Fish","doi":"10.1109/S3S.2013.6716579","DOIUrl":null,"url":null,"abstract":"In this work, a radiation hardened low-voltage memory cell for ultra-low power operation is proposed. The proposed 13T bitcell is implemented in a standard 0.18μm CMOS process and is shown to tolerate upsets with charge deposits as high as 500 fC through a dual-driven internal self-correction mechanism.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"173 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A 13T radiation hardened SRAM bitcell for low-voltage operation\",\"authors\":\"L. Atias, A. Teman, A. Fish\",\"doi\":\"10.1109/S3S.2013.6716579\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work, a radiation hardened low-voltage memory cell for ultra-low power operation is proposed. The proposed 13T bitcell is implemented in a standard 0.18μm CMOS process and is shown to tolerate upsets with charge deposits as high as 500 fC through a dual-driven internal self-correction mechanism.\",\"PeriodicalId\":219932,\"journal\":{\"name\":\"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)\",\"volume\":\"173 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/S3S.2013.6716579\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/S3S.2013.6716579","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5

摘要

本文提出了一种用于超低功耗工作的抗辐射低压存储单元。所提出的13T位电池采用标准的0.18μm CMOS工艺实现,通过双驱动内部自校正机制,可以承受高达500 fC的电荷沉积。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 13T radiation hardened SRAM bitcell for low-voltage operation
In this work, a radiation hardened low-voltage memory cell for ultra-low power operation is proposed. The proposed 13T bitcell is implemented in a standard 0.18μm CMOS process and is shown to tolerate upsets with charge deposits as high as 500 fC through a dual-driven internal self-correction mechanism.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信