Study on random telegraph noise of gate-ail-around poly-Si junctionless nanowire transistors

In this work we study the random telegraph noise (RTN) characteristics of short-channel gate-all-around (GAA) poly-Si junctionless (JL) nanowire (NW) transistors. The test devices were fabricated with I-line-based lithography in combination with novel spacer-etching techniques for aggressively shrinking the channel dimension. Based on the tiny nanowire channel and short-channel length, we are able to detect clear RTN signals as the gate voltage is sufficiently large. Location of the trap responsible for the RTN is estimated to be 1.13 nm within the gate oxide away from the oxide/channel interface.