改进CMRR的低功耗CMOS运算跨导放大器

2020 32nd International Conference on Microelectronics (ICM) Pub Date : 2020-12-14 DOI:10.1109/ICM50269.2020.9331501

Nedson J. Maia, A. D. R. Sánchez, R. Moreno, T. Pimenta, L. H. C. Ferreira

{"title":"改进CMRR的低功耗CMOS运算跨导放大器","authors":"Nedson J. Maia, A. D. R. Sánchez, R. Moreno, T. Pimenta, L. H. C. Ferreira","doi":"10.1109/ICM50269.2020.9331501","DOIUrl":null,"url":null,"abstract":"This work proposes a new low power Operational Transconductance Amplifier (OTA) topology. The rejection to common-mode signals is achieved by adding parallel transistors to input MOS transistors in order to increase the Common Mode Rejection Ratio (CMRR). It achieves a gain of 87.34 dB at 9.65 μW power consumption. The article presents a comparison to other OTA topologies. The proposed OTA was designed for the IBM 0.13 μm CMOS technology.","PeriodicalId":243968,"journal":{"name":"2020 32nd International Conference on Microelectronics (ICM)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A Low Power CMOS Operational Transconductance Amplifier with Improved CMRR\",\"authors\":\"Nedson J. Maia, A. D. R. Sánchez, R. Moreno, T. Pimenta, L. H. C. Ferreira\",\"doi\":\"10.1109/ICM50269.2020.9331501\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work proposes a new low power Operational Transconductance Amplifier (OTA) topology. The rejection to common-mode signals is achieved by adding parallel transistors to input MOS transistors in order to increase the Common Mode Rejection Ratio (CMRR). It achieves a gain of 87.34 dB at 9.65 μW power consumption. The article presents a comparison to other OTA topologies. The proposed OTA was designed for the IBM 0.13 μm CMOS technology.\",\"PeriodicalId\":243968,\"journal\":{\"name\":\"2020 32nd International Conference on Microelectronics (ICM)\",\"volume\":\"78 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-12-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 32nd International Conference on Microelectronics (ICM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICM50269.2020.9331501\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 32nd International Conference on Microelectronics (ICM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICM50269.2020.9331501","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

本文提出了一种新的低功耗跨导运算放大器(OTA)拓扑结构。对共模信号的抑制通过在输入MOS晶体管上增加并联晶体管来实现，以提高共模抑制比(CMRR)。在9.65 μW的功耗下实现了87.34 dB的增益。本文提供了与其他OTA拓扑的比较。该OTA是基于IBM 0.13 μm CMOS技术设计的。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A Low Power CMOS Operational Transconductance Amplifier with Improved CMRR

This work proposes a new low power Operational Transconductance Amplifier (OTA) topology. The rejection to common-mode signals is achieved by adding parallel transistors to input MOS transistors in order to increase the Common Mode Rejection Ratio (CMRR). It achieves a gain of 87.34 dB at 9.65 μW power consumption. The article presents a comparison to other OTA topologies. The proposed OTA was designed for the IBM 0.13 μm CMOS technology.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2020 32nd International Conference on Microelectronics (ICM)

自引率

0.00%

发文量