Cost models for large file memory DRAMs with ECC and bad block marking

We present cost models appropriate for large file memory DRAMs that exploit error-correcting codes, redundant elements and bad block marking in order to reduce the average cost per working bit. Many different fault-tolerance methods have been considered previously for DRAMs but, because of the constraints of conventional commodity memory, only a few methods, such as redundant rows and columns, have entered wide-spread use. Our research on file memory breaks from past work by relaxing the requirements that random-access be fast and that shipped devices contain 100% of the nominal working bit capacity. We show that, under the relaxed requirements of file memory, the greater potential efficiencies of large ECC codewords and bad block marking may become cost-effective. These file memory techniques may thus be a way of accelerating the economic production of 256 Mbit and 1 Gbit DRAMs.