Delay and power consumption of fault tolerant data busses in VDSM technology

In Very Deep-submicron (VDSM) systems, the scaling of ULSI ICs has increased the sensitivity of CMOS technology to cause various noise mechanismssuch as power supply noise, crosstalk noise, leakage noise, etc. In VDSM technology distance between the data bus lines is reduced, so coupling capacitance is dominating factor. Unfortunately, in VDSM systems, the coupling capacitance is of magnitude several times larger than the loading capacitance. The coupling capacitance causes logical malfunction, delay faults, and power consumption on long on-chip data buses. An important effect of the coupling capacitance is Cross talk. Crosstalk is mainly dependent on several factors: drive strength, wire length/spacing, edge rate and propagation duration. The crosstalk noise produces from the coupling capacitance. Such faults may affect data on data bus. To avoid this condition and to guarantee signal integrity on the on-chip communication, a fault tolerant bus can be adopted. This could be achieved by implementing error-correcting codes (ECCs), providing on-line correction and do not require data retransmission. The 4,8,16, and 32-bit data bus is implemented in 180nm, 120nm, and 65nm technologies using Bsim4 model. For reliable transmission of the data ECC techniques is placed on the data bus. We employed a Hamming code and Dual rail as ECC for 4,8,16 and 32-bit fault tolerant data bus. This is implemented in 180nm, 120nm and 65nm technology. The simulation results show that Average power varies from 0.737mw to 0.176mw, and Maximum delay varies from 0.143nsec to 0.077nsec, for hamming 4 bit ECC, Average power varies from 2.135mw to 0.365mw and Maximum delay varies from 0.385nsec to 0.192nsec for hamming 8 bit ECC, Average power varies from 2.288mw to 0.377mw and Maximum delay varies from 0.721nsec to 0.353nsec for hamming 16 bit ECC, Average power varies from 3.064mw to 0.437mw and Maximum delay varies from 1.562nsec to 0.796nsec for hamming 32 bit ECC. The simulation results show that Average power varies from 0.206mw to 0.0459mw, and Maximum delay varies from 0.241nsec to 0.133nsec, for dual rail 4 bit ECC, Average power varies from 0.417mw to 0.0768mw and Maximum delay varies from 0.479nsec to 0.262nsec for dual rail 8 bit ECC, Average power varies from 0.726mw to 0.156mw and Maximum delay varies from 1.026nsec to 0.554nsec for dual rail 16 bit ECC, Average power varies from 0.926mw to 0.108mw and Maximum delay varies from 2.129nsec to 1.145nsec for dual rail 32 bit ECC respectively.