用于94 GHz收发器的超低功耗组件

2016 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2016-10-01 DOI:10.1109/CSICS.2016.7751076

Seong-Kyun Kim, R. Maurer, A. Simsek, M. Urteaga, M. Rodwell

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引用次数: 4

摘要

我们提出了一个完全集成的94 GHz收发器前端，采用130 nm / 1.1 THz fmax InP HBT工艺。通过低电压设计和高晶体管增益获得低功耗。该集成电路是为多功能双极化相控阵设计的。在1.5 V集电极偏压下，双极化同时接收模式下，集成电路的增益为21 dB， <;噪声系数为9.3 dB，功耗为39mw，而在纵横双工发射模式下，收发器输出功率为5dbm，增益为22db，功耗为40mw。在1.0 V偏置下，双极化同时接收模式下，IC的增益为22.7 dB， <;噪声系数8.9 dB，能耗26 mW。

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Ultra-Low-Power Components for a 94 GHz Transceiver

We present a fully-integrated 94 GHz transceiver front-end in a 130 nm / 1.1 THz fmax InP HBT process. Low power is obtained through low-voltage design and high transistor gain. The IC is designed for multi-function, dual-polarization phased arrays. At 1.5 V collector bias, in dual-polarization simultaneous receiving mode, the IC has 21 dB gain, <; 9.3 dB noise figure, and consumes 39 mW, while in transmitting mode with time-duplexed vertical and horizontal outputs, the transceiver achieves 5 dBm output power, 22 dB gain, and consumes 40 mW. At 1.0 V bias, in dual-polarization simultaneous receiving mode, the IC has 22.7 dB gain, <; 8.9 dB noise figure, and consumes 26 mW.

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2016 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)

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