利用finfet保持奇偶校验的可逆设计

2019 1st International Conference on Signal Processing, VLSI and Communication Engineering (ICSPVCE) Pub Date : 2019-03-01 DOI:10.1109/ICSPVCE46182.2019.9092779

Lokesh Mahor, Anurag Chauhan, P. Tiwari

{"title":"利用finfet保持奇偶校验的可逆设计","authors":"Lokesh Mahor, Anurag Chauhan, P. Tiwari","doi":"10.1109/ICSPVCE46182.2019.9092779","DOIUrl":null,"url":null,"abstract":"In this article we have developed parity preserving logic with the help of FinFET using reversible logic. Parity preserving reversibility allows the design to be fault tolerant as well as power efficient. Performance of the proposed design is validated by implementing full adder and ALU using FinFET with Cadence Virtuoso at 10nm. The design is approximately 50% better than the previously proposed designs along with preserving parity and reversibility.","PeriodicalId":335856,"journal":{"name":"2019 1st International Conference on Signal Processing, VLSI and Communication Engineering (ICSPVCE)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Parity Preserving Reversible Design Using FinFETs\",\"authors\":\"Lokesh Mahor, Anurag Chauhan, P. Tiwari\",\"doi\":\"10.1109/ICSPVCE46182.2019.9092779\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this article we have developed parity preserving logic with the help of FinFET using reversible logic. Parity preserving reversibility allows the design to be fault tolerant as well as power efficient. Performance of the proposed design is validated by implementing full adder and ALU using FinFET with Cadence Virtuoso at 10nm. The design is approximately 50% better than the previously proposed designs along with preserving parity and reversibility.\",\"PeriodicalId\":335856,\"journal\":{\"name\":\"2019 1st International Conference on Signal Processing, VLSI and Communication Engineering (ICSPVCE)\",\"volume\":\"46 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-03-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 1st International Conference on Signal Processing, VLSI and Communication Engineering (ICSPVCE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICSPVCE46182.2019.9092779\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 1st International Conference on Signal Processing, VLSI and Communication Engineering (ICSPVCE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSPVCE46182.2019.9092779","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

在本文中，我们利用可逆逻辑，利用FinFET开发了奇偶保持逻辑。奇偶保持可逆性允许设计是容错以及节能。通过使用FinFET和Cadence Virtuoso在10nm下实现全加法器和ALU，验证了所提出设计的性能。该设计比以前提出的设计大约好50%，同时保留了奇偶性和可逆性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Parity Preserving Reversible Design Using FinFETs

In this article we have developed parity preserving logic with the help of FinFET using reversible logic. Parity preserving reversibility allows the design to be fault tolerant as well as power efficient. Performance of the proposed design is validated by implementing full adder and ALU using FinFET with Cadence Virtuoso at 10nm. The design is approximately 50% better than the previously proposed designs along with preserving parity and reversibility.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2019 1st International Conference on Signal Processing, VLSI and Communication Engineering (ICSPVCE)

自引率

0.00%

发文量