Test Scheduling for Low Transition Reusable LFSR based BIST in 3-D Stacked ICs

Test Scheduling is a major bottleneck in reducing the test time for 3D stacked ICs, as the test which can be applied simultaneously in pre-bond testing may have to be applied in a different cycle due to the impending resource constraint in the post-bond testing. In this paper, a reusable Low transition BIST for 3D stacked ICs are proposed which can schedule the tests in both pre-bond and post-bond testing. Furthermore, an Improved Skyline Algorithm is used to further organize the tests. The complete test scheduling framework was applied to various ISCAS-85 and 89 benchmark circuits. From the results, it could be observed that the pseudo-Random Generator used in BIST framework is driven by Reseeded-Bit-Swapping LFSR (RBS-LFSR) which has reduced the amount of switching power dissipated from the circuit up to 25%. The BIST designs were validated at different modes of operation and the area, power overhead due to BIST is found to be negligible. With the use of Modified Skyline Algorithm the test time approximately reduced up to 29%.