{"title":"嵌入式控制系统并行执行的简单一对一架构","authors":"R. Nakamura, F. Arakawa, M. Edahiro","doi":"10.1109/CPSNA.2014.13","DOIUrl":null,"url":null,"abstract":"We propose in this paper a simple architecture for efficient execution of embedded control systems using a model-based design to which automatic parallelization is also applicable. This architecture makes use of the advantages of embedded control systems in the sense of parallel execution, and reduces their disadvantages by incurring minimal overhead from task scheduling and inter-task communication. With a model predictive control application, our architecture achieves communication latency 20 times faster than in current real-time OS communication methods for many cores. Moreover, our architecture achieves a speed-up for 64 cores that is 40 times that in single core execution, while its performance scalability is saturated up to 32 cores in real-time OS communication.","PeriodicalId":254175,"journal":{"name":"2014 IEEE International Conference on Cyber-Physical Systems, Networks, and Applications","volume":"43 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Simple One-to-One Architecture for Parallel Execution of Embedded Control Systems\",\"authors\":\"R. Nakamura, F. Arakawa, M. Edahiro\",\"doi\":\"10.1109/CPSNA.2014.13\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We propose in this paper a simple architecture for efficient execution of embedded control systems using a model-based design to which automatic parallelization is also applicable. This architecture makes use of the advantages of embedded control systems in the sense of parallel execution, and reduces their disadvantages by incurring minimal overhead from task scheduling and inter-task communication. With a model predictive control application, our architecture achieves communication latency 20 times faster than in current real-time OS communication methods for many cores. Moreover, our architecture achieves a speed-up for 64 cores that is 40 times that in single core execution, while its performance scalability is saturated up to 32 cores in real-time OS communication.\",\"PeriodicalId\":254175,\"journal\":{\"name\":\"2014 IEEE International Conference on Cyber-Physical Systems, Networks, and Applications\",\"volume\":\"43 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-08-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 IEEE International Conference on Cyber-Physical Systems, Networks, and Applications\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CPSNA.2014.13\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE International Conference on Cyber-Physical Systems, Networks, and Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CPSNA.2014.13","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Simple One-to-One Architecture for Parallel Execution of Embedded Control Systems
We propose in this paper a simple architecture for efficient execution of embedded control systems using a model-based design to which automatic parallelization is also applicable. This architecture makes use of the advantages of embedded control systems in the sense of parallel execution, and reduces their disadvantages by incurring minimal overhead from task scheduling and inter-task communication. With a model predictive control application, our architecture achieves communication latency 20 times faster than in current real-time OS communication methods for many cores. Moreover, our architecture achieves a speed-up for 64 cores that is 40 times that in single core execution, while its performance scalability is saturated up to 32 cores in real-time OS communication.