贝叶斯网络在FPGA电路中的实现

Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Pub Date : 2006-06-22 DOI:10.1109/MIXDES.2006.1706677

Z. Kulesza, W. Tylman

{"title":"贝叶斯网络在FPGA电路中的实现","authors":"Z. Kulesza, W. Tylman","doi":"10.1109/MIXDES.2006.1706677","DOIUrl":null,"url":null,"abstract":"The paper presents a novel approach to the implementation of Bayesian network - an implementation in an FPGA circuit. The opportunities and problems connected with the parallel-processing approach of the FPGA circuit are discussed. Modifications of the computation algorithm that are needed due to limited computational capabilities are described. Details of the construction of the main computational blocks are also depicted","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"34 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":"{\"title\":\"Implementation Of Bayesian Network In FPGA Circuit\",\"authors\":\"Z. Kulesza, W. Tylman\",\"doi\":\"10.1109/MIXDES.2006.1706677\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The paper presents a novel approach to the implementation of Bayesian network - an implementation in an FPGA circuit. The opportunities and problems connected with the parallel-processing approach of the FPGA circuit are discussed. Modifications of the computation algorithm that are needed due to limited computational capabilities are described. Details of the construction of the main computational blocks are also depicted\",\"PeriodicalId\":318768,\"journal\":{\"name\":\"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.\",\"volume\":\"34 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-06-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"14\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MIXDES.2006.1706677\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MIXDES.2006.1706677","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 14

摘要

本文提出了一种实现贝叶斯网络的新方法——在FPGA电路中的实现。讨论了FPGA电路并行处理方法带来的机遇和问题。描述了由于计算能力有限而需要对计算算法进行的修改。还描述了主要计算块的构造细节

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Implementation Of Bayesian Network In FPGA Circuit

The paper presents a novel approach to the implementation of Bayesian network - an implementation in an FPGA circuit. The opportunities and problems connected with the parallel-processing approach of the FPGA circuit are discussed. Modifications of the computation algorithm that are needed due to limited computational capabilities are described. Details of the construction of the main computational blocks are also depicted

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Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.

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