{"title":"基于28nm CMOS的135ghz 24gb /s直接数字解调16-QAM接收机","authors":"Carl D’heer, P. Reynaert","doi":"10.1109/ESSCIRC55480.2022.9911340","DOIUrl":null,"url":null,"abstract":"This paper presents a 135 GHz direct-digital demodulation 16-QAM receiver. A direct-conversion RF front-end is combined with an analog PAM-4 decoder to achieve efficient 16-QAM demodulation without needing a high-speed multi-bit ADC. The receiver, implemented in 28nm CMOS, demonstrates a conversion gain of 25 dB and integrated DSB noise figure better than 10dB. A 24Gb/s 16-QAM signal was detected and directly demodulated on-chip with a power consumption of 175mW.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 135 GHz 24 Gb/s Direct-Digital Demodulation 16-QAM Receiver in 28 nm CMOS\",\"authors\":\"Carl D’heer, P. Reynaert\",\"doi\":\"10.1109/ESSCIRC55480.2022.9911340\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a 135 GHz direct-digital demodulation 16-QAM receiver. A direct-conversion RF front-end is combined with an analog PAM-4 decoder to achieve efficient 16-QAM demodulation without needing a high-speed multi-bit ADC. The receiver, implemented in 28nm CMOS, demonstrates a conversion gain of 25 dB and integrated DSB noise figure better than 10dB. A 24Gb/s 16-QAM signal was detected and directly demodulated on-chip with a power consumption of 175mW.\",\"PeriodicalId\":168466,\"journal\":{\"name\":\"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)\",\"volume\":\"54 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-09-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC55480.2022.9911340\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC55480.2022.9911340","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 135 GHz 24 Gb/s Direct-Digital Demodulation 16-QAM Receiver in 28 nm CMOS
This paper presents a 135 GHz direct-digital demodulation 16-QAM receiver. A direct-conversion RF front-end is combined with an analog PAM-4 decoder to achieve efficient 16-QAM demodulation without needing a high-speed multi-bit ADC. The receiver, implemented in 28nm CMOS, demonstrates a conversion gain of 25 dB and integrated DSB noise figure better than 10dB. A 24Gb/s 16-QAM signal was detected and directly demodulated on-chip with a power consumption of 175mW.
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