基于可靠性感知仿真流程的6T-SRAM单元老化统计仿真

2015 45th European Solid State Device Research Conference (ESSDERC) Pub Date : 2015-11-12 DOI:10.1109/ESSDERC.2015.7324758

R. Hussin, L. Gerrer, J. Ding, Liping Wang, S. Amoroso, B. Cheng, D. Reid, P. Weckx, Marko Simicic, J. Franco, A. Vanderheyden, D. Vanhaeren, N. Horiguchi, B. Kaczer, A. Asenov

{"title":"基于可靠性感知仿真流程的6T-SRAM单元老化统计仿真","authors":"R. Hussin, L. Gerrer, J. Ding, Liping Wang, S. Amoroso, B. Cheng, D. Reid, P. Weckx, Marko Simicic, J. Franco, A. Vanderheyden, D. Vanhaeren, N. Horiguchi, B. Kaczer, A. Asenov","doi":"10.1109/ESSDERC.2015.7324758","DOIUrl":null,"url":null,"abstract":"This work present the last development of a statistical reliability aware simulation flow from transistors to circuits. A TCAD calibration methodology based on statistical measurement of a 60nm bulk MOSFET is presented. Statistical compact models of fresh and aged transistors are extracted form large ensembles of TCAD simulations results. Compact models representing intermediate stages of degradation, not captured in the TCAD simulations, are interpolated using a proprietary compact model generator. Statistical simulations results for a 6T-SRAM cell aging are presented following various aging scenario for both static noise margin and intrinsic write time.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Statistical simulations of 6T-SRAM cell ageing using a reliability aware simulation flow\",\"authors\":\"R. Hussin, L. Gerrer, J. Ding, Liping Wang, S. Amoroso, B. Cheng, D. Reid, P. Weckx, Marko Simicic, J. Franco, A. Vanderheyden, D. Vanhaeren, N. Horiguchi, B. Kaczer, A. Asenov\",\"doi\":\"10.1109/ESSDERC.2015.7324758\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work present the last development of a statistical reliability aware simulation flow from transistors to circuits. A TCAD calibration methodology based on statistical measurement of a 60nm bulk MOSFET is presented. Statistical compact models of fresh and aged transistors are extracted form large ensembles of TCAD simulations results. Compact models representing intermediate stages of degradation, not captured in the TCAD simulations, are interpolated using a proprietary compact model generator. Statistical simulations results for a 6T-SRAM cell aging are presented following various aging scenario for both static noise margin and intrinsic write time.\",\"PeriodicalId\":332857,\"journal\":{\"name\":\"2015 45th European Solid State Device Research Conference (ESSDERC)\",\"volume\":\"49 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-11-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 45th European Solid State Device Research Conference (ESSDERC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSDERC.2015.7324758\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 45th European Solid State Device Research Conference (ESSDERC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.2015.7324758","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

这项工作展示了从晶体管到电路的统计可靠性感知仿真流程的最新发展。提出了一种基于统计测量的60nm块体MOSFET的TCAD校准方法。从TCAD仿真结果的大集合中提取了新晶体管和旧晶体管的统计紧凑模型。表示中间退化阶段的紧凑模型，在TCAD模拟中没有捕获，使用专有的紧凑模型生成器进行插值。在静态噪声裕度和固有写时间两种老化情况下，给出了6T-SRAM单元老化的统计仿真结果。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Statistical simulations of 6T-SRAM cell ageing using a reliability aware simulation flow

This work present the last development of a statistical reliability aware simulation flow from transistors to circuits. A TCAD calibration methodology based on statistical measurement of a 60nm bulk MOSFET is presented. Statistical compact models of fresh and aged transistors are extracted form large ensembles of TCAD simulations results. Compact models representing intermediate stages of degradation, not captured in the TCAD simulations, are interpolated using a proprietary compact model generator. Statistical simulations results for a 6T-SRAM cell aging are presented following various aging scenario for both static noise margin and intrinsic write time.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2015 45th European Solid State Device Research Conference (ESSDERC)

自引率

0.00%

发文量