IC DEFECTS-BASED TESTABILITY ANALYSIS

High quality IC design involves not only performance and silicon area, but also testability. Product quality, measured by low dejects levels (as low as 100 p.p.m.), requires that test patterns must detect nearly all circuit faults caused by likely physical defects. This requires a careful examination of the testability of the physical design, and its enhancement. The purpose of this contribution is to present a methodology for physical testability evaluation, and to demonstrate its usefulness. The methodology allows realistic fault extraction and classification, and the identification of hard to detect faults, their layout location and physical origin, prior to simulation. Measures of physical testability and fault hardness are introduced. When possible, suggestions for design improvement by layout reconfiguration, are provided, as a better solution than simple test improvement, either by test pattern refinement, or by using more sophisticated detection techniques, like current testing. Simulation results, with several design examples, show that layout styles exhibit characteristic pat.terns, in terms of t,he incidence of faults caused by the different, physical defects. Hence, for each layout style, the sensivity of physical designs to each physical defect can be analysed and decreased. Moreover, simulation results with a new cell library demonstrate that physical design improvements can significantly enhance the circuit’s qualit,y and testability.