A Novel Digital Etch Technique for p-GaN Gate HEMT

We demonstrate the digital etching (DE) process to fabricated E-mode p-GaN/AIGaN/GaN HEMT. DE process comprising low power oxygen (02) plasma oxidizing and low power boron trichloride (BCl3) plasma etching to selectively remove p-GaN layer. The atomic layer etching (ALE) has an etching rate of 1.62 nm/cycle to achieved depth of 70nm. The 5-µm source-drain offset length (LSD) device with Ni/Au gate metal demonstrated 365 mAlmm drain current density with threshold voltage (VTH) of +1.8V, on/off current ratio of 1.6×10⁶, breakdown voltage (BV) of 154V, and static on-resistance (RON) of 8.47 Ω.mm. The 20-µm LSD device with Ni/Au gate metal demonstrated 211 mA/mm drain current density with VTH of +2V, and on/off current ratio of 1. 2×10⁶, BV of 426V, and static RON of 17.3 Ω.mm.