A 12 ns, CMOS programmable logic device for combinatorial applications

A 12-ns, 400-mW programmable logic device implemented in two-layer metal, 0.8-μm CMOS EPROM technology is presented. The device is optimized for combinatorial applications and provides programmable input macrocells for latched, registered, or combinatorial inputs. This device provides 1200 equivalent gates in a 28-pin package, with 13 inputs, 12 I/Os, one VCC, and two VSS pins. Each I/O pin, in addition to the programmable input register, has a product-term-controlled XOR gate for dynamic output polarity control and a control mux for output enable. The part has selective, nonvolatile power-down of unused circuitry. The sense amplifier is optimized for speed and power and is compensated for process, temperature, and pattern variations. The device uses a regulated substrate bias generator optimized for the process to improve latchup immunity and performance