External loop unrolling of image processing programs: optimal register allocation for RISC architectures

Most of today's image processing applications rely on the computing power delivered by RISC processors. RISC processors are load/store architectures in the sense that their instructions can process only operands present in CPU registers. Finding a register allocation that reduces or possibly minimizes the number of load/store instructions is one of the main concerns in the efficient implementation of image processing programs on load/store architectures. The execution speedups delivered by source program transformations and in particular by external loop unrolling transformation applied to image processing programs-largely experimented in our previous works-led us to undertake an analytical investigation on the register allocation delivered by such source program transformations. In this paper we present a proof that external loop unrolling asymptotically achieves an optimal register allocation for a large class of image processing programs.