Bit serial pattern generation and response compaction using arithmetic functions

Adders, subtracters, and multipliers, which are available in many data paths, can be utilized to generate patterns and compact test responses. While previous work studied configurations which process patterns and test responses that have the size of a data word, this paper investigates bit serial pattern generators and compactors as they are required, for example, to test a random logic portion of the circuit by means of a scan path. Different arithmetic pattern generators are proposed that can produce a variety of bit strings with long periods and similar fault coverage as pseudorandom bit strings. The paper also analyzes aliasing in arithmetic compactors that process the test responses bit by bit. An upper bound on the limiting value of the aliasing probability for large test lengths can be computed very efficiently. The results of this paper open up a new range of applications for arithmetic BIST.