{"title":"模拟公司ip的基于仿真的分层规模和偏差","authors":"F. Javid, R. Iskander, M. Louërat","doi":"10.1109/BMAS.2009.5338891","DOIUrl":null,"url":null,"abstract":"This paper presents a simulation-based hierarchical sizing and biasing tool for analog integrated circuits design. The tool allows the designer to express the sizing procedure in terms of sizing and biasing operators. These operators are technology independent, hence the documented procedure can be easily ran over different technologies. A procedure has been proposed for a single-ended two-stage operational amplifier and evaluated over 130nm, 65nm and 45nm technologies. The results prove the efficiency of the proposed tool.","PeriodicalId":169567,"journal":{"name":"2009 IEEE Behavioral Modeling and Simulation Workshop","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"Simulation-based hierarchical sizing and biasing of analog firm IPs\",\"authors\":\"F. Javid, R. Iskander, M. Louërat\",\"doi\":\"10.1109/BMAS.2009.5338891\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a simulation-based hierarchical sizing and biasing tool for analog integrated circuits design. The tool allows the designer to express the sizing procedure in terms of sizing and biasing operators. These operators are technology independent, hence the documented procedure can be easily ran over different technologies. A procedure has been proposed for a single-ended two-stage operational amplifier and evaluated over 130nm, 65nm and 45nm technologies. The results prove the efficiency of the proposed tool.\",\"PeriodicalId\":169567,\"journal\":{\"name\":\"2009 IEEE Behavioral Modeling and Simulation Workshop\",\"volume\":\"20 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-11-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 IEEE Behavioral Modeling and Simulation Workshop\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/BMAS.2009.5338891\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE Behavioral Modeling and Simulation Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BMAS.2009.5338891","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Simulation-based hierarchical sizing and biasing of analog firm IPs
This paper presents a simulation-based hierarchical sizing and biasing tool for analog integrated circuits design. The tool allows the designer to express the sizing procedure in terms of sizing and biasing operators. These operators are technology independent, hence the documented procedure can be easily ran over different technologies. A procedure has been proposed for a single-ended two-stage operational amplifier and evaluated over 130nm, 65nm and 45nm technologies. The results prove the efficiency of the proposed tool.
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