Leveraging Virtual Prototype Models for Hardware Verification of an Accelerated Network Packet Processing Engine

This paper describes the co-simulation methodology adopted for hardware verification of a next generation network packet processing engine (Advanced I/O Processor or AIOP) utilizing virtual prototype models developed originally for software verification. Though co-simulation strategies are common in verification of stand-alone processors, they have seldom been used for mega-modules and SoC, which consist of large number of cores and accelerators like the AIOP. The cosimulation platform containing the AIOP functional model is used as a dynamic scoreboard in the top-level Universal Verification Methodology (UVM) test-bench. Since functional models are untimed or loosely-timed, the primary challenge here is to maintain synchronization between the design-under-test (DUT) and the functional model. This paper describes in detail the synchronization challenges encountered while running multicore software and how they were solved with minimal sacrifice to verification quality. Using this methodology, we unearthed more than 15 critical bugs in the DUT as well as large number of issues in the software libraries and functional models.