基于分层监督/强化学习方法的MPSoC运行紧急控制

F. Maurer, Bryan Donyanavard, A. Rahmani, N. Dutt, A. Herkersdorf
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引用次数: 3

摘要

mpsoc在运行时越来越依赖于自适应资源管理策略,以便在执行复杂的应用程序工作负载时有效地利用资源。特别是,对足够的计算性能和功率/能源效率约束的冲突需求使得期望的应用程序目标难以实现。我们提出了一种分层的、跨层的硬件/软件资源管理器,能够适应不断变化的工作负载和系统动态,而无需初始知识。管理器使用基于规则的强化学习分类器表(lct)和基于存档的备份策略作为叶子控制器。lct直接操纵和执行MPSoC构建块操作参数,以探索和优化潜在的冲突系统需求(例如,在保持功率约束的同时满足性能目标)。主管将系统需求和应用程序目标转换为每个lct的目标函数(例如,每秒核心指令数(IPS))。因此,管理者管理低层LCT控制器可能出现的紧急行为,以响应1)操作策略之间的切换(例如,性能最大化vs功率最小化;2)不断变化的应用需求。这个分层管理器利用了软件管理器(实现灵活性)和硬件学习器(允许快速有效的优化)的双重好处。在FPGA原型上的实验证实了我们的方法能够在严格遵守给定功率限制的情况下,在运行时识别优化的MPSoC操作参数。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Emergent Control of MPSoC Operation by a Hierarchical Supervisor / Reinforcement Learning Approach
MPSoCs increasingly depend on adaptive resource management strategies at runtime for efficient utilization of resources when executing complex application workloads. In particular, conflicting demands for adequate computation performance and power-/energy-efficiency constraints make desired application goals hard to achieve. We present a hierarchical, cross-layer hardware/software resource manager capable of adapting to changing workloads and system dynamics with zero initial knowledge. The manager uses rule-based reinforcement learning classifier tables (LCTs) with an archive-based backup policy as leaf controllers. The LCTs directly manipulate and enforce MPSoC building block operation parameters in order to explore and optimize potentially conflicting system requirements (e.g., meeting a performance target while staying within the power constraint). A supervisor translates system requirements and application goals into per-LCT objective functions (e.g., core instructions-per-second (IPS). Thus, the supervisor manages the possibly emergent behavior of the low-level LCT controllers in response to 1) switching between operation strategies (e.g., maximize performance vs. minimize power; and 2) changing application requirements. This hierarchical manager leverages the dual benefits of a software supervisor (enabling flexibility), together with hardware learners (allowing quick and efficient optimization). Experiments on an FPGA prototype confirmed the ability of our approach to identify optimized MPSoC operation parameters at runtime while strictly obeying given power constraints.
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