{"title":"具有字错误检测和校正的RAM自调整输出数据压缩","authors":"S. Musin, A. A. Ivaniuk, V. Yarmolik","doi":"10.1109/MIXDES.2007.4286220","DOIUrl":null,"url":null,"abstract":"This paper presents the reliability improvement of self-adjusting output data compression technique. Our theoretical investigation showed that compression of both address and data allows to achieve single word error detection and correction, and double word error detection. Possible built-in self-test architecture is proposed.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"29 26","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Self-Adjusting Output Data Compression for RAM with Word Error Detection and Correction\",\"authors\":\"S. Musin, A. A. Ivaniuk, V. Yarmolik\",\"doi\":\"10.1109/MIXDES.2007.4286220\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the reliability improvement of self-adjusting output data compression technique. Our theoretical investigation showed that compression of both address and data allows to achieve single word error detection and correction, and double word error detection. Possible built-in self-test architecture is proposed.\",\"PeriodicalId\":310187,\"journal\":{\"name\":\"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems\",\"volume\":\"29 26\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-06-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MIXDES.2007.4286220\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MIXDES.2007.4286220","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Self-Adjusting Output Data Compression for RAM with Word Error Detection and Correction
This paper presents the reliability improvement of self-adjusting output data compression technique. Our theoretical investigation showed that compression of both address and data allows to achieve single word error detection and correction, and double word error detection. Possible built-in self-test architecture is proposed.