Issues in fault modelling and testing of micropipelines

Micropipelines, suggested by Ivan Sutherland (1989) form an elegant scheme for asynchronous implementation of pipelined circuits. The authors analyse the faulty behavior of micropipelines and propose schemes for testing. They suggest that the control part of the micropipeline is concurrently testable during normal operation and that test pattern generation for the data part logic can be reduced to that for combinational circuits, with a simple modification only in the test application method. Testing latches require a two-pattern test which can be generated using test pattern generation techniques for combinational circuits.<>