{"title":"10gb /s ATM数据同步器","authors":"T.Y.K. Wong, J. Sitch, S. McGarry","doi":"10.1109/GAAS.1995.528959","DOIUrl":null,"url":null,"abstract":"A data synchroniser based on an analog controlled data delay driven by a clock to data phase detector is reported. The synchroniser is fabricated in an HBT processes and runs at 10 Gb/s with 200 ps delay range.","PeriodicalId":422183,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995","volume":"75 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 10 Gb/s ATM data synchroniser\",\"authors\":\"T.Y.K. Wong, J. Sitch, S. McGarry\",\"doi\":\"10.1109/GAAS.1995.528959\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A data synchroniser based on an analog controlled data delay driven by a clock to data phase detector is reported. The synchroniser is fabricated in an HBT processes and runs at 10 Gb/s with 200 ps delay range.\",\"PeriodicalId\":422183,\"journal\":{\"name\":\"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995\",\"volume\":\"75 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-10-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/GAAS.1995.528959\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GAAS.1995.528959","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A data synchroniser based on an analog controlled data delay driven by a clock to data phase detector is reported. The synchroniser is fabricated in an HBT processes and runs at 10 Gb/s with 200 ps delay range.