Designing and Implementation of 32-bit 5 stage Pipelined MIPS based RISC Processor Capable of Resolving Data Hazards

The main objective is to design and implement a 5-stage pipelined 32-bit High performance RISC Processor with MIPS architecture which is also capable in detecting and resolving Data Hazards. The Processor is designed as an instantiation of submodules using Verilog HDL. Pipelining is incorporated between each block thus boosting the processor speed. The other various modules being used are Memories for Instruction and as well as Data, Control Unit, Arithmetic and Logical Unit, Controller, Buffers etc. The processor also incorporates the design that detects Hazards and Data forwarding unit which detects and resolves all kind of data hazards and provides effective operation of the pipeline. The proposed designed model has better performance in terms of Delay, Power and Area when compared with other state of the art designs. The power consumption of 0.023W was achieved by incorporating above techniques. The design synthesis and critical factors like power, frequency, area, and propagation delay is analyzed using Cadence Genus tool and simulated using Model Sim.