模拟和混合信号毫米波SiGe BiCMOS电路:技术现状和未来缩放

S. Voinigescu, S. Shopov, J. Hoffman, K. Vasilakopoulos
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引用次数: 6

摘要

本文综述了未来无线回程和1Tb/s光纤系统的100+Gb/s SiGe BiCMOS电路和系统架构的最新工作,并探讨了这些应用的未来SiGe BiCMOS节点的技术要求和基准电路缩放。其中讨论的电路包括240GHz信号源,输出功率超过7dBm, 108GS/s轨道和保持放大器,120Gb/s TIA, 135GHz带宽线性低噪声放大器,80GHz带宽线性分布式驱动器,输出摆幅超过6Vpp,以及120GS/s功率- dac测试车,差分输出摆幅超过6Vpp。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Analog and Mixed-Signal Millimeter-Wave SiGe BiCMOS Circuits: State of the Art and Future Scaling
This paper reviews recent work on 100+Gb/s SiGe BiCMOS circuits and system architectures for future wireless backhaul and 1Tb/s fiber-optics systems, and explores technology requirements and benchmark circuit scaling in future SiGe BiCMOS nodes for these applications. Among the circuits discussed are a 240GHz signal source with over 7dBm output power, a 108GS/s track and hold amplifier, 120Gb/s TIA, 135GHz bandwidth linear low-noise amplifier, 80GHz bandwidth linear distributed driver with over 6Vpp output swing, and a proof-ofconcept 120GS/s power-DAC test vehicle with 6Vpp differential output swing.
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