Modeling and characterization of the system-level Power Delivery Network for a dual-core ARM Cortex-A57 cluster in 28nm CMOS

Power delivery is a well-known challenge for high-end microprocessor systems. Comparatively, mobile computing platforms typically consume order-of-magnitude lower currents, but economic and volume constraints limit the quality of the Power Delivery Network. In addition, the trend towards GHz+ operating frequencies and the ubiquity of low-power techniques such as clock-gating and power-gating, make these systems susceptible to pathological AC transients. Consequently, mobile computing systems are ultimately limited by power-delivery. In this paper, we present the system-level Power Delivery Network (PDN) modeling, analysis and measurement results on a dual-core 64bit ARM Cortex-A57 compute cluster in 28nm CMOS. We present a comprehensive analysis of the PDN by characterizing the individual contribution of each constituent i.e. the PCB, package and the die. We present frequency- and time-domain simulation results and correlate that with measurement (both on-chip and off-chip). Our results demonstrate how complex software and micro-architectural interactions can trigger PDN resonances that ultimately lead to system failure.