{"title":"基于fpga的电力线通道高速仿真系统","authors":"M. Babić, K. Dostert","doi":"10.1109/ISPLC.2005.1430517","DOIUrl":null,"url":null,"abstract":"The development and test of powerline communication (PLC) systems require standardized test beds that allow the real-time emulation of channels in the laboratory. Typical powerline channel properties, such as transfer function and the noise scenario must be covered. This paper presents the development of a system to perform these tasks.","PeriodicalId":153251,"journal":{"name":"International Symposium on Power Line Communications and Its Applications, 2005.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"An FPGA-based high-speed emulation system for powerline channels\",\"authors\":\"M. Babić, K. Dostert\",\"doi\":\"10.1109/ISPLC.2005.1430517\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The development and test of powerline communication (PLC) systems require standardized test beds that allow the real-time emulation of channels in the laboratory. Typical powerline channel properties, such as transfer function and the noise scenario must be covered. This paper presents the development of a system to perform these tasks.\",\"PeriodicalId\":153251,\"journal\":{\"name\":\"International Symposium on Power Line Communications and Its Applications, 2005.\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-04-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Symposium on Power Line Communications and Its Applications, 2005.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISPLC.2005.1430517\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Symposium on Power Line Communications and Its Applications, 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPLC.2005.1430517","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An FPGA-based high-speed emulation system for powerline channels
The development and test of powerline communication (PLC) systems require standardized test beds that allow the real-time emulation of channels in the laboratory. Typical powerline channel properties, such as transfer function and the noise scenario must be covered. This paper presents the development of a system to perform these tasks.