Implementation of a Low-power N-bit Hybrid Carry Select Adder with Sum-Carry Selection

Recently, the digital circuitry requires a reduction in space and power by optimizing the time with an increase in performance. Adders serve as the building blocks of the basic components of digital circuits. So, the performance of adders must be improved to enhance the performance of real-world integrated circuits. This article is focused on implementation of novel architecture of hybrid carry select adder (CSLA) utilizing full carry generation (FCG), full sum generation (FSG), half carry generation (HCG), and half sum generation (HSG) blocks, which is named as Hybrid CSLA. Further, the N-bit Hybrid-CSLA is implemented using reconfigurable properties with square root additions through modified sum carry selection (MSCS). Further, the Carry and Sum output generation consumes less propagation time by utilizing multiplexer switching logic, which selects the full sum bits and carry bits in high-speed manner. The simulation results show that the proposed Hybrid CSLA resulted in improved area, delay and power consumptions as compared to the basics adders and state-of-art approaches.