纳米电子电路中多数/少数门逻辑掩蔽能力的数学估计

Padmanabhan Balasubramanian, R. T. Naayagi
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引用次数: 0

摘要

在纳米电子电路合成中,多数门和逆变器构成了基本的组合逻辑原语。本文推导了在纳米电子数字电路合成中广泛应用的多数门逻辑掩蔽能力估计的数学公式。推导出的用于评估多数门逻辑掩蔽能力的数学公式适用于少数门,并与非门、与与非门、或与非或门和异或与非或门等传统门的逻辑掩蔽能力进行了比较。从本研究工作中可以推断,多数/少数门的逻辑屏蔽能力与异或/异或门相似,并且随着扇入的增加,多数/少数门的逻辑屏蔽能力也随之增加。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Mathematical estimation of logical masking capability of majority/minority gates used in nanoelectronic circuits
In nanoelectronic circuit synthesis, the majority gate and the inverter form the basic combinational logic primitives. This paper deduces the mathematical formulae to estimate the logical masking capability of majority gates, which are used extensively in nanoelectronic digital circuit synthesis. The mathematical formulae derived to evaluate the logical masking capability of majority gates holds well for minority gates, and a comparison with the logical masking capability of conventional gates such as NOT, AND/NAND, OR/NOR, and XOR/XNOR is provided. It is inferred from this research work that the logical masking capability of majority/minority gates is similar to that of XOR/XNOR gates, and with an increase of fan-in the logical masking capability of majority/minority gates also increases.
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