0.15 /spl mu/m栅极对InAlAs/InGaAs hemt输出电导的降低

Proceedings of 8th International Conference on Indium Phosphide and Related Materials Pub Date : 1996-04-21 DOI:10.1109/ICIPRM.1996.492284

H. Heiss, D. Xu, S. Kraus, M. Sexl, G. Bohm, G. Trankle, G. Weimann

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引用次数: 1

摘要

本文通过优化晶格匹配InAlAs/InGaAs高电子迁移率晶体管(HEMTs)的层结构和横向栅极凹槽宽度，来降低输出电导和扭结效应。极低的输出电导小于30 mS/mm，使得栅极长度为0.51 /spl mu/m时，f/sub max/-值(最大稳定增益)超过320 GHz。

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Reduction of the output conductance in InAlAs/InGaAs HEMTs with 0.15 /spl mu/m gates

We have optimized the layer structure and the width of lateral gate recess in lattice matched InAlAs/InGaAs High Electron Mobility Transistors (HEMTs) to reduce the output conductance and kink-effect. Very low output conductances less than 30 mS/mm lead to excellent f/sub max/-values (maximum stable gain) of more than 320 GHz for gate lengths of 0.51 /spl mu/m.

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Proceedings of 8th International Conference on Indium Phosphide and Related Materials

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