Distributed Layout Verification Using Sequential Software and Standard Hardware

This paper describes a new algorithm for parallel design verification. Its data model is that of tlhe data flow methodology and is based on the partitioning of the design verification cycle into independent tasks that can be run concurrently. The signihance of this methodology is that, unlike other concepts that connot use the existing sequential code and can only run on a an expensive specialpurpose hardware, the new approach does not require any code development and can be accommlodated by a ,standard Unix distributed network or a miiltiprocessor . The paper presents experimental results for performing 52 design rule checks on 1.3 million polygons (12 layers) on both a multiprocessor configuration and a distributed network.