面积高效的ESD设计，使用分布在I/O单元环外的电源钳

2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD) Pub Date : 2016-09-01 DOI:10.1109/EOSESD.2016.7592534

S. Maeda, Masanori Tanaka, Yoko Otsuka, Akinobu Watanabe, Masayuki Tsukuda, Y. Morishita

{"title":"面积高效的ESD设计，使用分布在I/O单元环外的电源钳","authors":"S. Maeda, Masanori Tanaka, Yoko Otsuka, Akinobu Watanabe, Masayuki Tsukuda, Y. Morishita","doi":"10.1109/EOSESD.2016.7592534","DOIUrl":null,"url":null,"abstract":"We propose new ESD design concept using power clamps distributed outside I/O cell ring, which enables the reduction of chip area by the removal of dead space in the chip core area with no degradation of ESD robustness. Our effective design was demonstrated with 40nm MCU test-chip.","PeriodicalId":239756,"journal":{"name":"2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Area-efficient ESD design using power clamps distributed outside I/O cell ring\",\"authors\":\"S. Maeda, Masanori Tanaka, Yoko Otsuka, Akinobu Watanabe, Masayuki Tsukuda, Y. Morishita\",\"doi\":\"10.1109/EOSESD.2016.7592534\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We propose new ESD design concept using power clamps distributed outside I/O cell ring, which enables the reduction of chip area by the removal of dead space in the chip core area with no degradation of ESD robustness. Our effective design was demonstrated with 40nm MCU test-chip.\",\"PeriodicalId\":239756,\"journal\":{\"name\":\"2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)\",\"volume\":\"85 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EOSESD.2016.7592534\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EOSESD.2016.7592534","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

摘要

我们提出了新的ESD设计概念，使用分布在I/O单元环外的电源钳，通过去除芯片核心区域的死区来减少芯片面积，而不会降低ESD稳健性。我们的有效设计在40nm MCU测试芯片上得到了验证。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Area-efficient ESD design using power clamps distributed outside I/O cell ring

We propose new ESD design concept using power clamps distributed outside I/O cell ring, which enables the reduction of chip area by the removal of dead space in the chip core area with no degradation of ESD robustness. Our effective design was demonstrated with 40nm MCU test-chip.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)

自引率

0.00%

发文量