具有基频抵消的11mw正交三倍频器

2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2010-03-01 DOI:10.1109/SMIC.2010.5422967

Chien-Chung Tsai, Derric Chang, Huan-Sheng Chen, C. Kuo

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引用次数: 4

摘要

采用次谐波混频器结构设计了一种低功耗正交三倍频器。该电路采用CMOS 0.180um技术实现。三频器功耗11.5mW，输出缓冲器功耗43.1mW，电源电压均为1.8V。在输出频率为4.5GHz时，基波谐波抑制比(HRR1)达到35dB以上，转换增益达到−4.2dB。整个芯片面积占1.4×1.1 mm2。

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A 11-mW quadrature frequency tripler with fundamental cancellation

A low-power quadrature frequency tripler is designed by using the sub-harmonic mixer configuration. The circuit is implemented in CMOS 0.180um technology. The frequency tripler consumes 11.5mW, while the output buffers consumes 43.1mW, all with supply voltage of 1.8V. The fundamental Harmonic Rejection Ratio (HRR1) achieves more than 35dB, and the conversion gain achieves −4.2dB at output frequency of 4.5GHz. The entire chip area occupied 1.4×1.1 mm2.

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2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)

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