{"title":"HDTV视频解码器运动补偿的并行实现","authors":"C.L. Lee","doi":"10.1109/ISCE.1997.658349","DOIUrl":null,"url":null,"abstract":"A parallel motion compensation architecture is proposed for an HDTV video decoder. It is based on block layer picture partitioning. It adds a routing module between decoding engines and block layer memory modules. It can resolve memory access conflicts and avoid extra access delay. The simultaneous access and identical addressing properties make the control scheme very simple. The routing network can be implemented by a simple interconnection network. This architecture is applicable to macroblock structures of 4:2:0, 4:2:2 and 4:4:4 chroma formats. This architecture can be one of the solutions for a parallel HDTV video decoder.","PeriodicalId":393861,"journal":{"name":"ISCE '97. Proceedings of 1997 IEEE International Symposium on Consumer Electronics (Cat. No.97TH8348)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1997-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":"{\"title\":\"Parallel implementation of motion-compensation for HDTV video decoder\",\"authors\":\"C.L. Lee\",\"doi\":\"10.1109/ISCE.1997.658349\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A parallel motion compensation architecture is proposed for an HDTV video decoder. It is based on block layer picture partitioning. It adds a routing module between decoding engines and block layer memory modules. It can resolve memory access conflicts and avoid extra access delay. The simultaneous access and identical addressing properties make the control scheme very simple. The routing network can be implemented by a simple interconnection network. This architecture is applicable to macroblock structures of 4:2:0, 4:2:2 and 4:4:4 chroma formats. This architecture can be one of the solutions for a parallel HDTV video decoder.\",\"PeriodicalId\":393861,\"journal\":{\"name\":\"ISCE '97. Proceedings of 1997 IEEE International Symposium on Consumer Electronics (Cat. No.97TH8348)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-12-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"13\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ISCE '97. Proceedings of 1997 IEEE International Symposium on Consumer Electronics (Cat. No.97TH8348)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISCE.1997.658349\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ISCE '97. Proceedings of 1997 IEEE International Symposium on Consumer Electronics (Cat. No.97TH8348)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCE.1997.658349","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Parallel implementation of motion-compensation for HDTV video decoder
A parallel motion compensation architecture is proposed for an HDTV video decoder. It is based on block layer picture partitioning. It adds a routing module between decoding engines and block layer memory modules. It can resolve memory access conflicts and avoid extra access delay. The simultaneous access and identical addressing properties make the control scheme very simple. The routing network can be implemented by a simple interconnection network. This architecture is applicable to macroblock structures of 4:2:0, 4:2:2 and 4:4:4 chroma formats. This architecture can be one of the solutions for a parallel HDTV video decoder.