Huang Lingyi, Zhu Uajiang, Qiu Yuling, Ye Qing, Chen Chaoshu, Chen Xiaodong, Su Zhenjiang, Liu Zhao, Wang Yuhui, Chen Xia
{"title":"亚微米和深亚微米ULSI的高速基库和宏库设计方法","authors":"Huang Lingyi, Zhu Uajiang, Qiu Yuling, Ye Qing, Chen Chaoshu, Chen Xiaodong, Su Zhenjiang, Liu Zhao, Wang Yuhui, Chen Xia","doi":"10.1109/ICSICT.1998.785932","DOIUrl":null,"url":null,"abstract":"This paper presents a high speed base library and macro library design methodology for submicron and deep submicron ULSI. Using the libraries, a 0.6 /spl mu/m CMOS high speed DSP chip is developed. To create the base and macro libraries, the effects of delay in interconnect wire and input slope were considered; the delay model was selected, the \"variable parameter\" cell and \"buried\" cell were used to correct a timing violation.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A high speed base library and macro library design methodology for submicron and deep submicron ULSI\",\"authors\":\"Huang Lingyi, Zhu Uajiang, Qiu Yuling, Ye Qing, Chen Chaoshu, Chen Xiaodong, Su Zhenjiang, Liu Zhao, Wang Yuhui, Chen Xia\",\"doi\":\"10.1109/ICSICT.1998.785932\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a high speed base library and macro library design methodology for submicron and deep submicron ULSI. Using the libraries, a 0.6 /spl mu/m CMOS high speed DSP chip is developed. To create the base and macro libraries, the effects of delay in interconnect wire and input slope were considered; the delay model was selected, the \\\"variable parameter\\\" cell and \\\"buried\\\" cell were used to correct a timing violation.\",\"PeriodicalId\":286980,\"journal\":{\"name\":\"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-10-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICSICT.1998.785932\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSICT.1998.785932","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A high speed base library and macro library design methodology for submicron and deep submicron ULSI
This paper presents a high speed base library and macro library design methodology for submicron and deep submicron ULSI. Using the libraries, a 0.6 /spl mu/m CMOS high speed DSP chip is developed. To create the base and macro libraries, the effects of delay in interconnect wire and input slope were considered; the delay model was selected, the "variable parameter" cell and "buried" cell were used to correct a timing violation.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
