{"title":"采用选择性氧化沉积技术的高性能非对称LDD MOSFET","authors":"T. Horiuchi, T. Homma, Y. Murao, K. Okumura","doi":"10.1109/VLSIT.1992.200662","DOIUrl":null,"url":null,"abstract":"It is shown that a 45% on-current increase can be achieved for an MOSFET without sacrificing hot carrier immunity by applying an asymmetric LDD sidewall spacer technology. The asymmetric spacer is fabricated by using a selective oxide deposition technique, which gives a wide design feasibility of implementing asymmetric structures in the CMOS process. The process requires no additional masking steps and is independent of wafer orientation. Based on an optimized asymmetric LDD design, 5-V operation of a 0.45- mu m nMOSFET is demonstrated. A simple on-current model for asymmetric LDD is also presented.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"22 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A high performance asymmetric LDD MOSFET using selective oxide deposition technique\",\"authors\":\"T. Horiuchi, T. Homma, Y. Murao, K. Okumura\",\"doi\":\"10.1109/VLSIT.1992.200662\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"It is shown that a 45% on-current increase can be achieved for an MOSFET without sacrificing hot carrier immunity by applying an asymmetric LDD sidewall spacer technology. The asymmetric spacer is fabricated by using a selective oxide deposition technique, which gives a wide design feasibility of implementing asymmetric structures in the CMOS process. The process requires no additional masking steps and is independent of wafer orientation. Based on an optimized asymmetric LDD design, 5-V operation of a 0.45- mu m nMOSFET is demonstrated. A simple on-current model for asymmetric LDD is also presented.<<ETX>>\",\"PeriodicalId\":404756,\"journal\":{\"name\":\"1992 Symposium on VLSI Technology Digest of Technical Papers\",\"volume\":\"22 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-06-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1992 Symposium on VLSI Technology Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.1992.200662\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1992 Symposium on VLSI Technology Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1992.200662","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
摘要
结果表明，在不牺牲热载流子抗扰度的情况下，应用非对称LDD侧壁间隔技术可以使MOSFET的导通电流增加45%。采用选择性氧化沉积技术制备了非对称间隔层，为在CMOS工艺中实现非对称结构提供了广泛的设计可行性。该工艺不需要额外的掩蔽步骤，并且与晶圆方向无关。基于优化的非对称LDD设计，演示了0.45 μ m nMOSFET的5v工作。本文还提出了一种简单的非对称LDD导通电流模型。
A high performance asymmetric LDD MOSFET using selective oxide deposition technique
It is shown that a 45% on-current increase can be achieved for an MOSFET without sacrificing hot carrier immunity by applying an asymmetric LDD sidewall spacer technology. The asymmetric spacer is fabricated by using a selective oxide deposition technique, which gives a wide design feasibility of implementing asymmetric structures in the CMOS process. The process requires no additional masking steps and is independent of wafer orientation. Based on an optimized asymmetric LDD design, 5-V operation of a 0.45- mu m nMOSFET is demonstrated. A simple on-current model for asymmetric LDD is also presented.<>
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