Cmos 500 Mbps/pin同步点对点链路接口

Proceedings of 1994 IEEE Symposium on VLSI Circuits Pub Date : 1994-06-09 DOI:10.1109/VLSIC.1994.586204

S. Sidiropoulos, C. Yang, Mark Horowitz

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引用次数: 21

摘要

本文介绍了一种用于多处理器互连网络的高速接口设计。为了实现更高的传输速率，接口利用1 V的电压摆幅，延迟线锁相环和时钟两侧的数据采样。采用0.8 pm CMOS技术制造的芯片在3.3 v电源下实现了700 Mbpdpin的传输速率。最坏情况下测量到的峰对峰时钟抖动是260 ps (63 ps RMS)。DLL和相关时钟占空比调节器占用的布局面积为460x800 pni2。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A Cmos 500 Mbps/pin Synchronous Point to Point Link Interface

This paper describes the design of a high speed interface for a multiprocessor interconnection network. To achieve higher transfer rates, the interface utilizes a voltage swing of 1 V, a Delay Line PLL and sampling of the data on both edges of the clock. Chips fabricated in a 0.8 pm CMOS technology achieve transfer rates of 700 Mbpdpin operating from a 3.3-V supply. Worst case measured peak-to-peak clock jitter is 260 ps (63 ps RMS). The layout area occupied by the DLL and the associated clock duty cycle adjuster is 460x800 pni2.

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Proceedings of 1994 IEEE Symposium on VLSI Circuits

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