Silicon on ferroelectric Tunnel FET (SOF-TFET) for low power application

In this paper, we propose and investigate a novel device structure for silicon-on-ferroelectric Tunnel FET (SOFTFET) based on the negative capacitance effect of the ferroelectric layer. The conduction mechanism of proposed device is based on the combined effect of two mechanisms namely, tunnelling and negative capacitance effect. Thus, it achieves a steep subthreshold slope (SS) of 13.9 mV/dec at room temperature. The various device performance parameters are investigated for the proposed structure using 2D TCAD simulations incorporating the drift-diffusion and 1-D Landau's models. Extensive device simulation proves that the silicon on ferroelectric Tunnel FET is a great improvement in terms of lower SS value and reduced hysteretic losses compared to the conventional TFET.