{"title":"高密度MTP逻辑NVM电源管理应用","authors":"Y. Roizin, E. Pikhay, V. Dayan, A. Heiman","doi":"10.1109/IMW.2009.5090593","DOIUrl":null,"url":null,"abstract":"We report a no mask adders embedded NVM (Y-Flash) having a record cell area which is suited for power management (PM) applications. The memory cell is a self- aligned asymmetric MOS transistor with drain capacitive coupling to the floating gate (FG) through a three- dimensional extension structure. Operation of the novel memory cell, array organization, design of NVM modules and Y-Flash reliability are addressed.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"High Density MTP Logic NVM for Power Management Applications\",\"authors\":\"Y. Roizin, E. Pikhay, V. Dayan, A. Heiman\",\"doi\":\"10.1109/IMW.2009.5090593\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We report a no mask adders embedded NVM (Y-Flash) having a record cell area which is suited for power management (PM) applications. The memory cell is a self- aligned asymmetric MOS transistor with drain capacitive coupling to the floating gate (FG) through a three- dimensional extension structure. Operation of the novel memory cell, array organization, design of NVM modules and Y-Flash reliability are addressed.\",\"PeriodicalId\":113507,\"journal\":{\"name\":\"2009 IEEE International Memory Workshop\",\"volume\":\"33 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-05-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 IEEE International Memory Workshop\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IMW.2009.5090593\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE International Memory Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMW.2009.5090593","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High Density MTP Logic NVM for Power Management Applications
We report a no mask adders embedded NVM (Y-Flash) having a record cell area which is suited for power management (PM) applications. The memory cell is a self- aligned asymmetric MOS transistor with drain capacitive coupling to the floating gate (FG) through a three- dimensional extension structure. Operation of the novel memory cell, array organization, design of NVM modules and Y-Flash reliability are addressed.