连续时间ΔΣ调制器中过量环路延迟补偿技术

2019 International Conference on Advanced Systems and Emergent Technologies (IC_ASET) Pub Date : 2019-03-01 DOI:10.1109/ASET.2019.8870998

Soumaya Azzouni, N. Khitouni, M. Bouhlel

{"title":"连续时间ΔΣ调制器中过量环路延迟补偿技术","authors":"Soumaya Azzouni, N. Khitouni, M. Bouhlel","doi":"10.1109/ASET.2019.8870998","DOIUrl":null,"url":null,"abstract":"The circuit non-idealities such as the opamp nonidealities, the clock jitter, comparator offset, DAC mismatch and the excess loop delay degrade the performance of the Continuous-time Sigma Delta Modulator. A study of a methods used for excess loop delay compensation is presented in this paper. The model used to analyze the techniques is a third order Single-bit Modulator with the Specification of LTE Network. The model have a sampling frequency at 459 MHz within 10 MHz.","PeriodicalId":216138,"journal":{"name":"2019 International Conference on Advanced Systems and Emergent Technologies (IC_ASET)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Excess loop delay compensation techniques in continuous-time ΔΣ modulators\",\"authors\":\"Soumaya Azzouni, N. Khitouni, M. Bouhlel\",\"doi\":\"10.1109/ASET.2019.8870998\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The circuit non-idealities such as the opamp nonidealities, the clock jitter, comparator offset, DAC mismatch and the excess loop delay degrade the performance of the Continuous-time Sigma Delta Modulator. A study of a methods used for excess loop delay compensation is presented in this paper. The model used to analyze the techniques is a third order Single-bit Modulator with the Specification of LTE Network. The model have a sampling frequency at 459 MHz within 10 MHz.\",\"PeriodicalId\":216138,\"journal\":{\"name\":\"2019 International Conference on Advanced Systems and Emergent Technologies (IC_ASET)\",\"volume\":\"97 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-03-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 International Conference on Advanced Systems and Emergent Technologies (IC_ASET)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASET.2019.8870998\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 International Conference on Advanced Systems and Emergent Technologies (IC_ASET)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASET.2019.8870998","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

电路的非理想性，如运放的非理想性、时钟抖动、比较器偏移、DAC失配和过量环路延迟降低了连续时间σ δ调制器的性能。本文研究了一种用于补偿多余环路延迟的方法。用于分析这些技术的模型是符合LTE网络规范的三阶单比特调制器。该模型的采样频率为459mhz，采样频率在10mhz以内。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Excess loop delay compensation techniques in continuous-time ΔΣ modulators

The circuit non-idealities such as the opamp nonidealities, the clock jitter, comparator offset, DAC mismatch and the excess loop delay degrade the performance of the Continuous-time Sigma Delta Modulator. A study of a methods used for excess loop delay compensation is presented in this paper. The model used to analyze the techniques is a third order Single-bit Modulator with the Specification of LTE Network. The model have a sampling frequency at 459 MHz within 10 MHz.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2019 International Conference on Advanced Systems and Emergent Technologies (IC_ASET)

自引率

0.00%

发文量