印加人:UltraSPARC的周期精确模型

Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors Pub Date : 1995-10-02 DOI:10.1109/ICCD.1995.528801

G. Maturana, James L. Ball, J. Gee, A. Iyer, J. M. O'Connor

{"title":"印加人:UltraSPARC的周期精确模型","authors":"G. Maturana, James L. Ball, J. Gee, A. Iyer, J. M. O'Connor","doi":"10.1109/ICCD.1995.528801","DOIUrl":null,"url":null,"abstract":"This paper describes a cycle accurate model of the UltraSPARC processor. The model is written in C++, and is built on top of a powerful programming framework with a built-in message-passing mechanism and a timing discipline for simulating concurrent modules. The goal was to help verify the processor by cross checking the RTL model at run time, as well as to provide accurate performance estimates. Because of Incas' much faster execution rate than the RTL, it was also used to model the UItraSPARC module in RTL simulations of the full system, for compiler and library tuning, and for diagnostics development.","PeriodicalId":281907,"journal":{"name":"Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":"{\"title\":\"Incas: a cycle accurate model of UltraSPARC\",\"authors\":\"G. Maturana, James L. Ball, J. Gee, A. Iyer, J. M. O'Connor\",\"doi\":\"10.1109/ICCD.1995.528801\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes a cycle accurate model of the UltraSPARC processor. The model is written in C++, and is built on top of a powerful programming framework with a built-in message-passing mechanism and a timing discipline for simulating concurrent modules. The goal was to help verify the processor by cross checking the RTL model at run time, as well as to provide accurate performance estimates. Because of Incas' much faster execution rate than the RTL, it was also used to model the UItraSPARC module in RTL simulations of the full system, for compiler and library tuning, and for diagnostics development.\",\"PeriodicalId\":281907,\"journal\":{\"name\":\"Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors\",\"volume\":\"11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-10-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"13\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCD.1995.528801\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCD.1995.528801","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 13

摘要

本文描述了UltraSPARC处理器的周期精确模型。该模型是用c++编写的，并且构建在一个强大的编程框架之上，该框架具有内置的消息传递机制和用于模拟并发模块的定时规则。目标是通过在运行时交叉检查RTL模型来帮助验证处理器，并提供准确的性能估计。由于Incas的执行速度比RTL快得多，它还被用于在完整系统的RTL模拟中为UItraSPARC模块建模，用于编译器和库调优，以及用于诊断开发。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Incas: a cycle accurate model of UltraSPARC

This paper describes a cycle accurate model of the UltraSPARC processor. The model is written in C++, and is built on top of a powerful programming framework with a built-in message-passing mechanism and a timing discipline for simulating concurrent modules. The goal was to help verify the processor by cross checking the RTL model at run time, as well as to provide accurate performance estimates. Because of Incas' much faster execution rate than the RTL, it was also used to model the UItraSPARC module in RTL simulations of the full system, for compiler and library tuning, and for diagnostics development.

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Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors

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