On the ESD Protection and Non-Fatal ESD Strike on Nano CMOS Devices

Electrostatic discharge (ESD) has been one of the major causes for the failure of electronic equipment and components and have attracted quite significant research efforts in minimizing the losses induced. Much tougher challenge comes up in the nano CMOS era. For the device technology itself, the aggressive scaling on gate length, high-k replacement of gate oxide, and the reduction of supply voltage have made the design window of ESD protection device be ever narrower. New ESD protection devices are yet to be developed for the 10 nm technology and beyond. For system and application level, the mobile devices we used right now are much vulnerable as they are more frequent to be exposed to various sources of ESD and power surges. Fatal ESD strike protection is always the primary design specification and should have been mostly fulfilled. The effects of non-fatal ESD strike has not attracted much attention yet. Recent experiment showed that the non-fatal ESD strikes at gate and drain can cause significant charge trapping and trap generation. It resulted in the device characteristic degradation and hence some reliability issues of CMOS circuits and the MOS-based ESD clamps. This review addresses all these issues in detail.