{"title":"各种隧道tfet的电性能评价","authors":"C. Huang, Tao-Yi Hung, Pei-Yu Wang, B. Tsui","doi":"10.1109/ISNE.2015.7132032","DOIUrl":null,"url":null,"abstract":"Tunnel field-effect transistor (TFET) is a promising device which has extraordinary performance on subthreshold swing and is feasible for ultralow power applications. However, one of the main factors of power dissipation and circuit delay among different designs of TFET, namely, parasitic capacitances, has not been discussed in detail. In this paper, parasitic capacitance of various types of TFETs are simulate and analyze.","PeriodicalId":152001,"journal":{"name":"2015 International Symposium on Next-Generation Electronics (ISNE)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Evaluation of electrical performance of various tunnel TFETs\",\"authors\":\"C. Huang, Tao-Yi Hung, Pei-Yu Wang, B. Tsui\",\"doi\":\"10.1109/ISNE.2015.7132032\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Tunnel field-effect transistor (TFET) is a promising device which has extraordinary performance on subthreshold swing and is feasible for ultralow power applications. However, one of the main factors of power dissipation and circuit delay among different designs of TFET, namely, parasitic capacitances, has not been discussed in detail. In this paper, parasitic capacitance of various types of TFETs are simulate and analyze.\",\"PeriodicalId\":152001,\"journal\":{\"name\":\"2015 International Symposium on Next-Generation Electronics (ISNE)\",\"volume\":\"65 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-05-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 International Symposium on Next-Generation Electronics (ISNE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISNE.2015.7132032\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 International Symposium on Next-Generation Electronics (ISNE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISNE.2015.7132032","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Evaluation of electrical performance of various tunnel TFETs
Tunnel field-effect transistor (TFET) is a promising device which has extraordinary performance on subthreshold swing and is feasible for ultralow power applications. However, one of the main factors of power dissipation and circuit delay among different designs of TFET, namely, parasitic capacitances, has not been discussed in detail. In this paper, parasitic capacitance of various types of TFETs are simulate and analyze.