High Speed Error-Detection and Correction Architectures for Viterbi Algorithm Implementation

The Viterbi algorithm is mostly used technique in the latest communication technology nodes to decode the convolutional codes. It is widely used in digital cellular, satellite communications and wireless Local Area Networks (LANs). In this work three different types of error detection schemes are discussed. Add-compare and select unit is iterative process in Viterbi decoder. Reduction of latency is achieved using the concept of Brent-Kung Adder. This scheme promotes the overall system performance by reducing the propagation delay. The merits of the proposed schemes are embedded with the design to detect and correct the transient and stuck-at-faults. The system functionality is verified using verilog HDL. The proposed architectures are simulated and synthesized in CADENCE [45nm technology] for Application Specific Integrated Circuit (ASIC) and FPGA (Virtex-6 family). In case of ASIC implementation, we achieve an improvement in delay by 12.39%, area by 11.43% for error detection and 5.83% in delay, 1.10% in area for error correction module. Also achieved an improvement in delay by 31.87%, area by 37.50% for error detection and 1.10% in delay, 5.83% in area for error correction over proposed error detection architecture in the FPGA implementation.