{"title":"寄存器约束下的定时和内存操作最小化的循环调度算法","authors":"F. Chen, S. Tongsima, E. Sha","doi":"10.1109/SIPS.1998.715820","DOIUrl":null,"url":null,"abstract":"We present a novel scheduling framework, called memory operation minimization rotation scheduling (MORS), for scheduling multi-dimensional applications subject to register constraints and other resource constraints. Under such constraints, MORS strives to shorten the schedule length while minimally inserting the load and store operations in the schedule to reduce the register requirement pressure. Experiments show that our approach is useful for reducing the schedule length without violating the register constraint of a target machine. Furthermore, the average reduction in the schedule length produced by these experiments reaches 36.6%.","PeriodicalId":151031,"journal":{"name":"1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Loop scheduling algorithm for timing and memory operation minimization with register constraint\",\"authors\":\"F. Chen, S. Tongsima, E. Sha\",\"doi\":\"10.1109/SIPS.1998.715820\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present a novel scheduling framework, called memory operation minimization rotation scheduling (MORS), for scheduling multi-dimensional applications subject to register constraints and other resource constraints. Under such constraints, MORS strives to shorten the schedule length while minimally inserting the load and store operations in the schedule to reduce the register requirement pressure. Experiments show that our approach is useful for reducing the schedule length without violating the register constraint of a target machine. Furthermore, the average reduction in the schedule length produced by these experiments reaches 36.6%.\",\"PeriodicalId\":151031,\"journal\":{\"name\":\"1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)\",\"volume\":\"19 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-10-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SIPS.1998.715820\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIPS.1998.715820","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Loop scheduling algorithm for timing and memory operation minimization with register constraint
We present a novel scheduling framework, called memory operation minimization rotation scheduling (MORS), for scheduling multi-dimensional applications subject to register constraints and other resource constraints. Under such constraints, MORS strives to shorten the schedule length while minimally inserting the load and store operations in the schedule to reduce the register requirement pressure. Experiments show that our approach is useful for reducing the schedule length without violating the register constraint of a target machine. Furthermore, the average reduction in the schedule length produced by these experiments reaches 36.6%.